1. Field of the Invention
The present invention relates to a package body for an integrated circuit, and more particularly to package bodies of various types such as a pin grid array type, a multi-tip module type, a land grid array type and the like and having a signal transmission structure such as a strip line structure, a microstrip line structure or the like.
2. Discussion of the Prior Art
In such, for instance, a conventional package body for an integrated circuit of the pin grid array type having a strip line structure, a chip cavity 11 is, as shown in FIG. 18, formed on a surface center of a ceramic substrate 10 so as to mount an integrated circuit 40 (see FIG. 19). Furthermore, within an annular portion 12 of the ceramic substrate 10 corresponding to an outer peripheral portion of the chip cavity 11, for instance eight high speed signal transmission lines 20a to 20h and plural low speed signal transmission lines are formed so as to extend radially from the peripheral wall of the chip cavity 11. In FIG. 18 only the low speed signal transmission lines 30a to 30u are illustrated. Each transmission line for the high speed signals and low speed signals is connected at one end portion thereof or a bonding pad to the integrated circuit 40 mounted in the chip cavity 11. For making constant a characteristic impedance of each of the high speed signal transmission lines 20a to 20h, each width of the high speed signal transmission lines 20a to 20h is maintained in a constant, and a ground pattern or an electric source pattern is provided above and below each of the high speed signal transmission lines 20a to 20h within the annular portion 12 of the ceramic substrate 10. In FIG. 19 only the electric source pattern or ground pattern for the high speed signal transmission line 20d is illustrated by the reference numerals 21 and 22. These constructions are also the same as those of each of the low speed signal transmission lines. In addition, the above-mentioned electric source pattern is used as a substitute for a ground pattern because it has the same effect as grounding for a high speed signal.
Furthermore, eight pins 50a to 50h for high speed signal input-output and plural pins for low speed signal input-output are securely arranged on a bottom surface of the annular portion 12 of the ceramic substrate 10 in a lattice configuration as terminal members for signal input-output respectively. In FIG. 18 only the pins 60a to 60u for low speed signal input-output are illustrated. The base portions of these pins are connected to the extending or other portions of the transmission lines for high speed signals and low speed signals through the corresponding via holes (In FIG. 19 only the via hole 23 is indicated.) respectively.
Incidentally, with such a package body for the integrated circuit, electrolytic plating is mostly done on the bonding pads and the pins for improvements of anti-corrosion and bonding with wires. In this case, plating tie-bars 70a to 70h for the high speed signal transmission lines and plating tie-bars for the low speed signal transmission lines (In FIG. 18 only the plating tie-bars 80a to 80u for the low speed signal transmission lines are illustrated.) are formed within the annular portion 12 of the ceramic substrate 10 from the extending portions of the corresponding transmission lines for high speed signals and low speed signals to the outer peripheral edge 12a of the ceramic substrate 10. These plating tie-bars are electrically connected in parallel to each other to for instance a conductor layer which is formed on the outer peripheral edge 12a with coating of conductive paste. Thus, electrolytically plating process of the bonding pads and pins are performed all at once, when an electric current flows through the conductor layer to the plating tie-bars to do electrolytically plating process.
After such electrolytically plating process, however, even if the above-mentioned conductor layer is removed from the outer peripheral edge 12a by grinding, the plating tie-bars for the transmission lines of the high and low speed signals are still remained within the annular portion 12 of the ceramic substrate 10. In this case, although no problems are present for the low speed signal transmission lines due to low frequencies of the low speed signals, there occur inevitably the following phenomena for the high speed signal transmission lines due to high frequencies of the high speed signals.
For easy understanding of the phenomena, a circuit construction (see FIG. 20) formed by the high speed signal transmission line 20d and plating tie-bar 70d connected through the via hole 23 to each other is represented by a distribution constant circuit, as shown in FIG. 21. In this case, a characteristic impedance of the high speed signal transmission line 20d is defined by an impedance Z01 composed of an inductance L=L1 and a capacitance C=C1 whereas a characteristic impedance of the plating tie-bar 70d is defined by an impedance Z02 composed of an inductance L=L2 and a capacitance C=C2. In general, taking account that the characteristic impedance of the high speed signal transmission line 20d is represented by ZO=(L/C).sup.1/2, a width of each high speed signal transmission line and distances between these high speed signal transmission lines and the corresponding ground patterns have been only to be designed in advance such that a characteristic impedance required based on properties of the integrated circuit is satisfied with Z01. Considering the above-mentioned distribution constant circuit with reference to the construction of FIG. 20, a high speed signal current i flowing into the pin 50d flows separately into both the high speed signal transmission line 20d and plating tie-bar 70d through the via hole 23. In this case, since an end of the plating tie-bar 70d which is not connected with the high speed signal transmission line 20d is an opened end, a partial current which has flowed into the plating tie-bar 70d is reflected at the opened end of the plating tie-bar 70d and returns to its connecting portion with the high speed signal transmission line 20d and then flows into the high speed signal transmission line 20d so as to join with the partial current flowing into the high speed signal transmission line 20d. This means that the more the above-mentioned joining timing delays or the more the length of the plating tie-bar 70d is long, the more the joined current of both the partial currents becomes considerably smaller than the high speed signal current i, because the partial current flowing through the high speed signal transmission line 20 d is flowing precedingly during return time of the partial current flowing through the plating tie-bar 70d.
In other words, considering that a parallel circuit is formed by Z01 and Z02, a synthetic characteristic impedance (hereinafter called as a synthetic characteristic impedance Z) of the distribution constant circuit formed by the above-mentioned separately flowing of the high speed signal current i is given by Z=Z01.multidot.Z02/(Z01+Z02). Thus, if for instance Z01=Z02, the synthetic characteristic impedance becomes Z=Z01/2, reducing to a half of the predetermined characteristic impedance Z01. Therefore, there occur the drawbacks that the actual characteristic impedance of the high speed signal transmission line 20d reduces remarkably more than the designed characteristic impedance due to influences of the impedance of the plating tie-bar 70d caused by flow of the high speed signal current i into the plating tie-bar 70d from the pin 50d. Meanwhile, if Z01 is large compared with Z02, the drawbacks is difficult to occur but it becomes necessary to narrow a width of each plating tie-bar. However, the width of each signal transmission line is designed to be considerably narrow, because of high density wiring of each signal transmission line. Thus, if the width of each plating tie-bar is further narrowed, there is the possibility that each plating tie-bar is broken. This means that it is difficult to resolve the above-mentioned drawbacks by extremely narrowing only the width of each plating tie-bar.
Incidentally, the present inventors have measured such phenomena with an oscilloscope by using Time Domain Reflection measurement method (hereinafter called as TDR measurement method.). The TDR measurement method is a method wherein a characteristic impedance on a certain location is measured in relation to a return transmission time of a signal between one certain and the other locations on a test sample. On the occasion of the measurement, the pin 50d has been removed and a measuring probe has been directly connected to the via hole 23. In this state, the above-mentioned phenomena have been measured with the TDR measurement method by flowing the high speed signal current i into the high speed signal transmission line 20d and plating tie-bar 70d through a measuring cable (a 50-ohm coaxial cable), the measuring probe and the via hole 23. Thus, a measured result shown in FIG. 22 has been obtained.
In this case, a designed characteristic impedance of the high speed signal transmission line 20d is assumed to be 50 ohms, and an end portion (a portion to be connected to the integrated circuit 40) of the same high speed signal transmission line 20d is assumed to be opened. In FIG. 22, the axis of abscissas indicates a return transmission time or a transmitting and reflecting location of the high speed signal current i whereas the axis of ordinates indicates characteristic impedances on each corresponding transmitting and reflecting location of the measuring cable, via hole 23, high speed signal transmission line 20d and plating tie-bar 70d. In this case, in FIG. 22, a region A corresponds to the measuring cable, and a region B corresponds to the measuring probe. A region C corresponds to the via hole 23, plating tie-bar 70d and high speed signal transmission line 20d , and a region D corresponds to an integrated circuit side end portion of the high speed signal transmission line 20d.
Referring to FIG. 22, the region A defines relationship between a return transmission time of the high speed signal current i till each location within the measuring cable and a characteristic impedance on each corresponding transmitting and reflecting location. And the region B defines relationship between a return transmission time of the high speed signal current i till each location within the measuring probe and a characteristic impedance on each corresponding transmitting and reflecting location. Furthermore, the region C defines relationship between a return transmission time of the high speed signal current i till each location between the tip portion of the via hole 23 and the one end portion or bonding pad of the high speed signal current i and a characteristic impedance on each corresponding transmitting and reflecting location. And the region D represents a characteristic impedance of the bonding pad which is maintained to be opened. While the characteristic impedance at the region D originally shows an infinitely great value, it gradually rises in relation to a response speed of the measuring instrument. In this case, with the region C it is recognized that the synthetic characteristic impedance lowers down to 28.7 ohms. This means that the characteristic impedance of the high speed signal transmission line 20d from the location of the pin 50d remarkably lowers compared with the designed characteristic impedance (50 ohms).
In contrast with this, it is considered to shorten a length of each plating tie-bar for the high speed signal transmission lines. However, because of construction of a transmitting circuit it is impossible that all of the pins arranged in the form of lattice configuration are located near the outer edge of the ceramic substrate 10. It is also not always possible to arrange the pins for high speed signal transmission near the outer edge of the ceramic substrate 10, because each location of the pins is determined in relation to design of the integrated circuit. Thus, shortening of the lengths of these plating tie-bars is limited of itself, so long as there premises the structure that the plating tie-bars for high speed signal transmission lines are connected to connecting portions between the corresponding via holes and corresponding high speed signal transmission lines respectively. As a result, it is impossible to resolve the drawbacks that the characteristic impedance of the high speed signal transmission line lowers, as previously described.